Aldec Active-HDL 8.3 SP1u1
Package of Active-HDL is a fully integrated development environment based on digital devices HDL text descriptions.
FPGA Design "Made easy"
Active-HDL is a Windows based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL / gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation flows, making it a seamless and flexible design and verification platform. Active-HDL supports industry leading FPGA devices, from Actel , Altera , Lattice , Quicklogic , Xilinx and more.
Multi-FPGA & EDA Tool Design Flow Manager
Graphical Design entry & editing
Code2Graphics and Graphics2Code
Import / Export Legacy Designs
Pre-compiled FPGA vendor libraries
High Performance Mixed-Language RTL Simulator
IEEE Language Support: VHDL, Verilog , SystemVerilog Design, SystemC
Automatic Testbench Generation
Advanced Debugging & Code Coverage
IP Encryption and Xilinx Secure IP support
ABV, Assertion-Based Verification (SVA, PSL, OVA)
DSP Co-simulation with MATLAB / Simulink
PCB Design Interface
Server Farm Manager
HTML and PDF Design Documentation