Aldec Active-HDL 9.1 (update 2) 9.1 2353.4205.02 x86 | 396MB
Active-HDL - an integrated development environment, modeling and verification projects for programmable logic devices (FPGA), developed by Aldec.
The software package allows you to describe the device using hardware description languages: VHDL, Verilog and SystemC, as well as using block diagrams or automaton graphs. Modeling project is a powerful multi-language simulator at gate and register transfer (RTL). Supported by joint work with programs MatLab and Simulink. In addition, the structure of the software package includes a number of tools to investigate the efficiency and make the optimization of the initial description of the project, as well as convert HDL-description in the graphical block diagrams and back. The built-in standard modules (IP-Core Generator) allows you to quickly and easily create projects of any complexity.
Process Manager supports the development of more than 120 products of the programmable logic and FPGA EDA throughout the entire development process, including a description of the project, its simulation, synthesis and implementation on the target platform. Due to the additional libraries installed Active-HDL supports the development of programmable devices under most of the leading developers such as Altera , Atmel , Lattice , Microsemi (Actel), Quicklogic , Xilinx and others.
Version: 9.1 Build 2353.4205.02
Developer: Aldec Inc.
Website Developer: www.aldec.com
System requirements: Windows 7/Vista/XP/2003 - (32/64-Bit)
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